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license.dat:
#windows license
FEATURE easepc translogic 4.000 permanent uncounted D6FFE5CAB3EF \
VENDOR_STRING="TEAM SLT" HOSTID=ANY
FEATURE ealepc translogic 4.000 permanent uncounted 382D0ED0
80E3 \
VENDOR_STRING="TEAM SLT" HOSTID=ANY
#below is linux/solaris
FEATURE ease translogic 4.00 permanent uncounted 9902172
D3B0F \
VENDOR_STRING="TEAM SLT" HOSTID=ANY
FEATURE eale translogic 4.00 permanent uncounted 3CC2323F5A59 \
VENDOR_STRING="TEAM SLT" HOSTID=ANY
file_id.diz:
│▓█████▀▀ ▀ │░█████ │░█████
▀▀▀▀▀▀▀▓█████ │▒█████ │▒█████▀▀ ▀
│▓█████ │▓█████ │▓█████ │▓█████ ▓█████
│▓█████▄▄▓█████▄│▓█████▄│▓█████▄▄▓█████▄ ▄
------------------------------------------
xx/04 06-29-2000
Ease and Eale v4.1R3 *For Solaris*
(c) Translogic
solitude.nfo:
│░█████████
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│▓█████████ │▓█████████ │▓█████████ │▓█████████ │▓█████████ a!b
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┌═══════════════════════════════════════════════════════════════════════════┐
│ SOLiTUDE PROUDLY PRESENTS: Ease and Eale v4.1R3 *For Solaris* - │
│ (c) Translogic │
├────────────────────────────────────┬──────────────────────────────────────┤
│ SUPPLiER........ TEAM SLT │ OPERATiNG SYSTEM....... Solaris │
│ CRACKER......... TEAM SLT │ RELEASE SiZE........... xx/
8;4 │
│ PACKER.......... TEAM SLT │ RELEASE DATE........... 06-29-2&
#48;00 │
│ GENRE........... HDL │ PROTECTION............. FlexLm │
│ TESTED BY....... TEAM SLT │ CRACK TYPE............. License │
├──────────────┬─────────────────────┴──────────────────────────────────────┘
│ RELEASE iNFO │
└──────────────┘
Ease and Eale v4.1R3 *For Solaris* (c) Translogic
Ease
Graphical HDL Entry Tool
Features & Benefits
-Graphical design environment with automated generation of hierarchical
VHDL or Verilog code
-Push-button import of legacy Verilog or VHDL designs and extraction of
graphical hierarchy of the design
-Adheres to state of the art Windows look and feel for intuitive operation
-Standards compliant (IEEE-1076-87&93 VHDL and IEEE-1364 Verilo
g)
-Design management through advanced browsers, version control and strict
library organization
-Extensive documentation capabilities
-Integrates smoothly with the industry's most popular simulators and
synthesis tools
-Platform independent database
-Integrated HDL language editor
-Hot error reporting
Translogic's EASE offers the best of both worlds with your choice of graphi
cal
or text based HDL entry. You don’t need to be a master of either Verilog o
r
VHDL. If you're creating a new design, just enter it using your mix of
graphics
and text. EASE automatically generates optimized HDL code for you in your
preferred language - VHDL or Verilog.
Block Diagram Editor
The block diagram editor allows you to decompose your system into functional
blocks. The block diagram editor supports automatic property propagation to
ensure consistency. Flexible and modular designs are developed through the
use
of generics and parameters. Automatic, incremental place and route of nets and
buses is supported in addition to manual place and route of blocks to allow a
fast, accurate and customized representation of your design.
Graphical Processes/Always Blocks
Facilitating an abstraction level in between block diagrams and plain HDL code,
EASE allows you to graphically represent VHDL processes or Verilog always
statements. They can be placed as a block in a block diagram along with VHDL
components or Verilog module instances, resulting in a much simpler design
hierarchy. This approach yields a more compact HDL description and visualizes
the data flow inside a single diagram.
State Diagram Editor
The state diagram editor supports Moore, Mealy and mixed state machines. A
ny
valid VHDL expression or Verilog statement can be used to define actions a
nd
transition conditions. Transitions can be synchronous or asynchronous; outputs
can be clocked or combinatorial. The state diagram editor supports a variety of
state assignment methods, including binary, gray, one-hot and two-hot. User
defined assignment is also possible. The HDL generated is optimized for time an
d
area for best possible synthesized design from leading synthesis tools.
Import Legacy Code
Automatically import VHDL or Verilog code with push-button ease and view
graphical hierarchy of the imported design. EASE preserves and documents the
original design, including concurrent statement blocks, increasing the ability
for others to understand the design. EASE can import IP in HDL format, which
you can then modify if needed (or consider it a black box), and regenerate
the
IP along with other code.
Design Management
EASE's comprehensive design management capabilities make designing a snap.
EASE
is entirely project oriented; it supports multiple projects per designer. EASE
facilitates proper multi-user behavior by use of links to other projects and is
organized to support source revision control systems. EASE features two browser
s:
the database browser and the hierarchy browser. The database browser provides
fast access to non graphical design objects such as package use, module bodies,
always blocks, comment text and declarations. The hierarchy browser is the
vehicle
for fast navigation of the design and shows the entire design hierarchy includi
ng
design alternatives. The status of each design element inside the hierarchy is
shown by green checkmark (OK), yellow question mark (Incomplete) and red cross
(Error). Shapes denote the type of block whereas colors denote design alternati
ves,
graphics or text. The hierarchy browser provides configuration management
through
the specification of hierarchical configurations and bindings.
Documentation
EASE offers extensive documentation capabilities to support your design pr
oject.
If you generate a design using EASE, documentation is available at the onset. I
n
addition, if you import existing VHDL or Verilog code, EASE can provide co
mplete
documentation for that design as well.
Hot Error Reporting
EASE benefits from the close integration to EALE, Translogic's HDL language
editor,
by enabling hot error reports. The verification report contains hot links direc
tly
to the correct spot in the diagram where the error occurred. This helps to easi
ly
trace errors in the design.
Standards Support
EASE's code generator produces HDL output conforming to IEEE-1076-8
7 and IEEE-1076-93
VHDL standards, as well as the IEEE-1364 Verilog standard. EASE also suppor
ts the
industry's most popular simulators and synthesis tools, as well as version
control
features when provided.
Eale
Graphical HDL Language Editor
Features & Benefits
-High performance, comprehensive HDL language editor
-Fully configurable for your design environment
-Supports Verilog, VHDL, and C design languages
-Standards compliant (IEEE-1076-87&93 VHDL and IEEE-1364 Verilo
g)
-Interfaces to the industry's most popular simulators and synthesis tools
-High-quality, affordable, cost-effective tool
-Supports Windows, Linux, Solaris and HP-UX platforms
Engineers who truly know the power of a high-level design language such as Veri
log
or VHDL, like to actually touch the code when they design. This means accessing
the code through a text editor, whether or not you're using a graphica
l description
in combination. Translogic's EALE is a comprehensive HDL language editor wh
ich
offers high productivity in a cost-effective tool for time-conscious designers.
Translogic's EALE Language Editor
A powerful HDL language editor helps you truly to access the nuances of your
preferred design language. EALE provides full access to industry-standard desig
n
languages, along with an extensive set of templates for customization.
EALE's Multiple Document Interface allows you to reuse existing pieces
of code
by simply cutting and pasting across multiple documents. Its built-in templates
offer automatic skeleton generation for specific parts of your design. And beca
use
it's tightly integrated with the industry's most popular simulators, it
provides
backannotation, so you can see precisely which lines of code contain errors.
EALE is extremely easy to read on-screen. It provides fully customizable o
ptions
such as color coding, automatic capitalization of keywords and automatic
indentation. It prints colors or greyscale, bold, italics, etc., so your hard c
opy
reflects exactly what's on screen.
EALE will set the standard in your company for text-oriented HDL design. I
t runs
on multiple platforms, so everyone can use the same software.
EALE is part of Translogic's EASE graphical entry tool, providing a compreh
ensive
design package. Whether you prefer to touch the code, or view graphical
representations, Translogic's HDL design tools provide a high-quality, affo
rdable,
cost-effective solution.
EALE's Comprehensive Capabilities
Translogic's EALE provides a complete package for your high-level design ne
eds,
including: Language Flexibility, Fully Configurable, Design Management, Do
cumentation
and Standards Support.
Language Flexibility
EALE supports VHDL, Verilog, C, and synthesis script languages. Plus, EALE is e
asily
configurable for other languages, so you can have access to the language of you
r
preference.
Fully Configurable
In addition to its language capabilities, EALE offers a number of customizable
options
to create a design environment that meets your needs. Synthesis templates, keyw
ord
templates, and user interface are easily tailored to your requirements. In addi
tion,
you can choose syntax coloring and in- and out-commenting of selected te&#
120;t, as well
as line numbering and indentation.
Design Management
The powerful EALE language editor provides multi-document editing capabilities.
You
can reuse existing files by cutting and pasting, and work with multiple de
signers on
one design. It also offers unique, full history unfolding undo/redo capability,
to
track changes made during the design process. EALE's on-line syntax br
owser makes it
easy to review countless lines of code in a short amount of time. And EALE is t
he
only HDL text editor to offer these capabilities also on a UNIX platform.
Documentation
EALE offers extensive documentation capabilities to support your design pr
oject. EALE
offers color coding, capitalization an indentation to make your numerous lines
of
code more readable.
Standards Support
Translogic's EALE language editor supports IEEE-1076-87 and IEEE-&#
49;076-93 VHDL
standards, as well as the IEEE-1364 Verilog standard. EALE also supports th
e
industry's most popular simulators and synthesis tools. EALE is tightly int
egrated
with ModelSim, Synplify and Leonardo Spectrum for hot error reporting.
┌═══════════════┐
│ iNSTALL NOTES │
└───────────────┘
Unzip, Unrar, Untar. Install. Put the license somewhere and point the
LM_License_File variable to it.
Enjoy!.
┌═══════════════════════════════════════════════════════════════════════════┐
│ SLT NEWS │ │
├──────────┘ │
│ The SLT Crew, is pleased to announce the two new divisions at SLT, │
│ SLT LINUX, and SLT SOLARIS - where we will get you the newest and │
│ best within those two operating systems, while still bringing you │
│ high quality utils for win9x/NT/win2k.
│
│ │
│ Linux & Solaris crackers, testers and suppliers are encouraged to apply
│
│ for trial membership. │
│ │
│ │
│ │
└───────────────────────────────────────────────────────────────────────────┘
┌═══════════════════════════════════════════════════════════════════════════┐
│ SLT GREETS │ │
├────────────┘ │
│ RBS, DOD, SCUM, DWP, CSWCN, HARVEST .. │
│ │
└───────────────────────────────────────────────────────────────────────────┘
┌═══════════════════════════════════════════════════════════════════════════┐
│ JOINING SLT │ │
├─────────────┘ │
│ │
│ We are seeking people able to: │
│ │
│ 1. Supply unreleased software.
│
│ │
│ 2. Crackers - We are seeking skilled crackers on WinNT and Linux
│
│ especially those with FlexLM and dongle experience, our crackers
│
│ work very close, and if you need to pickup some skills, we can │
│ help you gain them. │
│ │
│ 3. Testers, preferably with previous experience.
│
│ │
│ │
└───────────────────────────────────────────────────────────────────────────┘
┌═══════════════════════════════════════════════════════════════════════════┐
│ CONTACT SLT │ │
├────────────────┘ │
│ IRC : #SLT (EFNET) │
│ Email : removed for security reasons │
│ WWW : Coming Soon.. │
│ │
│───────────────────────────────────────────────────────────────────────────│
│ │
│ NFO Header by Antibody / Layout by valient │
│ (c) 1999 SOLiTUDE
│
│ │
└───────────────────────────────────────────────────────────────────────────┘
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